Skip Navigation Linksallegro



​​Allegro 電腦音樂軟體


The Cadence® Allegro® FPGA System Planner offers a complete, scalable technology for FPGA-PCB co-design that allows users to create an optimum correct-by-construction pin assignment. FPGA pin assignment is synthesized automatically based on user-specified, interface-based connectivity, FPGA device pin assignment rules, and placement of FPGAs on the PCB. With automatic pin assignment synthesis, users avoid manual error-prone processes while shortening the time to create initial pin assignment that accounts for FPGA placement on the PCB. This unique placement-aware pin assignment approach eliminates unnecessary physical design iterations that are inherent in manual approaches while shortening the design cycle time.

Cadence®Allegro®FPGA系統規劃器為FPGA-PCB共同設計提供了一個完整的、可擴展的技術,允許用戶創建一個最佳的正確構建pin分配。 FPGA pin分配是基於用戶指定和基於接口的連接、FPGA pin分配規則和FPGA在PCB上的放置自動合成的。通過自動pin分配合成,用戶避免手動易出錯的過程,同時縮短創建初始pin分配的時間,以解決在PCB上的放置問題。這種獨特的放置識別pin分配方法,消除了手動方法中固有的不必要的物理設計迭代,同時縮短了設計週期。​